Development of the industry's first high-performance serial bit error ratio tester (BERT) with advanced generation capabilities for jitter-tolerance testing (J-BERT) of serial gigabit devices at speeds to 12.5Gb/s has been reported by Agilent Technologies Inc., Palo Alto CA.

The N4903A provides the only complete jitter-tolerance test solution for fast, high-quality characterization of next-generation serial devices conforming to serial bus standards with data rates of 5Gb/s and beyond, expected by 2006, the firm says.

The increasing speed will cause significant signal integrity and jitter issues during the design and test of next-generation serial bus devices. In addition, new transmission techniques, such as spread spectrum clocking, make device performance characterization more difficult and time-consuming, Agilent says.

The N4903A provides calibrated jitter composition and automated jitter characterization in a single box and is compliant with the latest serial bus standards. It provides complete built-in and calibrated jitter composition for stressed eye testing of receivers. Automated and compliant testing covers all popular serial bus standards, such as PCI Express, SATA, Fibre Channel, FB-DIMM, CEI, Gigabit Ethernet and XFP.

"Jitter-tolerance testing is the most complex and time-consuming measurement that design teams of next-generation serial devices have to deal with," Siegfried Gross, Agilent vice president and general manager, Digital Verification Solutions division, says. The new BERT includes:

*Built-in, calibrated, automated and compliant jitter-tolerance testing with sources for PJ, RJ, BUJ, ISI and sinusoidal interference. This enables fast, high-precision stressed eye testing with more than 50 percent eye closure.

*Full support of complex data patterns of serial bus interfaces.

*Unpredictable traffic analysis with the bit recovery mode, enabling more realistic test scenarios. Complex training sequences can be set up with the new pattern sequencer easily, simplifying the test development process.

*Built-in CDR, new subrate clock outputs and spread-spectrum clocking (SSC), which significantly simplify the clock setup.

*Accurate characterization with clean eyes, 20ps transition times and 50mV analyzer sensitivity.